Embedded ball grid array substrate and manufacturing method thereof

ABSTRACT

Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2010-0089021, filed on Sep. 10, 2010, entitled “Embedded Ball GridArray Substrate And Manufacturing Method Thereof” which is herebyincorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to an embedded ball grid array substrateand a manufacturing method thereof.

2. Description of the Related Art

With the development of electronic industries, the integration of asemiconductor integrated circuit (IC) has been remarkably increased.Portable terminals in mobile communication fields serve only voicecommunication, short message transmission, etc., in the early stage.Recently, however, portable terminals have been increasingly expandedfrom basic communication functions, such as a game, data transmission,digital camera, music/moving picture file playing, or the like, to amultimedia service area.

Meanwhile, slimness and lightweight of a terminal are essentiallydemanded in consideration of portability of a portable terminalperforming a mobile communication function.

There are a packaging technology in a ball grid array (BGA) scheme and apackaging technology in a land grid array (WA) scheme in order toimprove the integration of circuit devices.

The packaging technology in the BGA scheme is a technology that fusessolder balls to bond a chip, in which a semiconductor integrated circuitis molded, to a substrate. The fused solder balls are used as input andoutput terminals of the semiconductor integrated circuit. In this case,a technology of configuring the input and output terminals of thesemiconductor integrated circuit as a solder pad provided on thesubstrate without fusing the solder balls is a packaging technology inan LGA scheme.

FIG. 1 shows a packaging scheme according to the prior art.

FIG. 1 is a cross-sectional view of a structure in which a resin ismolded on the substrate and a packaging is made in the ball grid arrayscheme.

In this case, integrated circuits and passive devices 12 are mounted ona substrate 11 and a molding part 15 covering the passive devices isformed. The molding part 15 can serve to protect a mounting device 12from external environments or effects and firmly fix the mounting device12 on the substrate 11.

In this case, since the integrated circuits and the passive devices aremounted on one surface of the substrate, there is a limitation inreducing a volume.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide an embeddedball grid array substrate capable of forming a cavity on a core layerand embedding a semiconductor chip in the formed cavity to reduce athickness, and a manufacturing method thereof.

An embedded ball grid array substrate according to a preferredembodiment of the present invention includes: a core layer made of aninsulating material and having a cavity therein; a semiconductor deviceembedded in the cavity of the core layer; a first circuit layer formedon one surface of the core layer and having a circuit pattern includinga wire bonding pad formed thereon; a second circuit layer formed on theother surface of the core layer and having a circuit pattern including asolder ball pattern formed thereon; and a wire electrically connectingthe semiconductor device to the wire bonding pad.

The embedded ball grid array substrate may further include a supportinglayer made of an insulating material and fixing the semiconductor deviceby being formed to surround the semiconductor device.

The core layer may include: a first insulating layer having one surfacecontacting the first circuit layer and including a cavity therein toembed the semiconductor device in the formed cavity; and a secondinsulating layer made of an insulating material and having one surfacecontacting the first insulating layer and the other surface contactingthe second circuit layer.

The embedded ball grid array substrate may further include a via holepenetrating through the core layer to electrically connect the firstcircuit layer to the second circuit layer.

The embedded ball grid array substrate may further include a firstsolder resist stacked on one surface of the first circuit layer; asecond solder resist stacked on one surface of the second circuit layer;and a molding layer covering the first solder resist layer.

According to another preferred embodiment of the present invention,there is provided a manufacturing method of an embedded ball grid arraysubstrate, including: (A) removing a copper clad of one surface of afirst insulating layer, after preparing a copper cladded laminate formedwith a copper clad at both sides of the first insulating layer andforming a cavity; (B) attaching a heat-resistant tape to an oppositesurface to a surface from which the copper clad of the copper cladlaminate is removed; (C) mounting a semiconductor device in a cavity ofthe copper clad laminate and stacking a second insulating layer and acopper clad on a surface from which the copper clad is removed; (D)forming a first circuit layer formed with a circuit pattern including awire bonding pad at a copper clad contacting the first insulating layerand forming a circuit pattern including a solder ball pad at a copperclad contacting the second insulating layer; and (E) bonding andelectrically connecting the semiconductor device to a wire bonding padby a wire.

The manufacturing method of the embedded ball grid array substrate mayfurther include after step (C), (F) forming a via hole penetratingthrough the first insulating layer and a second insulating layer.

The manufacturing method of the embedded ball grid array substrate mayfurther include after step (D), (G) stacking a first solder resist on afirst circuit layer and stacking a second solder resist on a secondcircuit layer; (H) forming holes at a position corresponding to the wirebonding pad of the first circuit layer at the first solder resist; and(I) forming holes at a position corresponding to the solder ball pad ofthe second circuit layer at the second solder resist.

At step (B), the heat-resistant tape may be a polyimide film.

Step (C) may include: (C-1) mounting the semiconductor device in thecavity of the copper clad laminate; (C-2) stacking the second insulatinglayer on a surface from which the copper clad is removed; (C-3) stackingthe copper clad on the second insulating layer by using a carrier; and(C-4) removing the carrier.

Step (D) may include: (D-1) stacking a dry film on a copper cladcontacting the first insulating layer and a copper clad contacting thesecond insulating layer; (D-2) forming a pattern corresponding to acircuit pattern of the first circuit layer including the wire bondingpad on the first dry film stacked on the copper clad contacting thefirst insulating layer and forming a pattern corresponding to a circuitpattern of the second circuit layer including the solder ball pad on thesecond dry film stacked on the copper clad contacting the secondinsulating layer; and (D-3) completing the first circuit layer and thesecond circuit layer formed with the circuit pattern including the wirebonding pad and the solder ball pad by etching the copper clad accordingto the pattern of the first dry film and the second dry film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a packaging scheme according to the prior art;

FIG. 2 is a structural diagram of an embedded ball grid array accordingto a first preferred embodiment of the present invention; and

FIGS. 3 to 16 are cross-sectional views showing a manufacturing methodof an embedded ball grid array substrate according to the firstpreferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various features and advantages of the present invention will be moreobvious from the following description with reference to theaccompanying drawings.

The terms and words used in the present specification and claims shouldnot be interpreted as being limited to typical meanings or dictionarydefinitions, but should be interpreted as having meanings and conceptsrelevant to the technical scope of the present invention based on therule according to which an inventor can appropriately define the conceptof the term to describe most appropriately the best method he or sheknows for carrying out the invention.

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings. In thespecification, in adding reference numerals to components throughout thedrawings, it is to be noted that like reference numerals designate likecomponents even though components are shown in different drawings.Further, in describing the present invention, a detailed description ofrelated known functions or configurations will be omitted so as not toobscure the gist of the present invention.

Hereinafter, a preferred embodiment of the present invention will bedescribed in detail with reference to the accompanying drawings.

FIG. 2 is a structural diagram of an embedded ball grid array accordingto a first exemplary embodiment of the present invention.

Referring to FIG. 2, an embedded ball grid array substrate according toa first preferred embodiment of the present invention includes a corelayer 110 made of an insulating material and having a cavity 110 aaincluded therein, a semiconductor device 120 embedded in the cavity 110aa of the core layer 110, a supporting layer 130 made of an insulatingmaterial and fixing the semiconductor device 120 by being formed tosurround the semiconductor device 120, a first circuit layer 140 aformed on the upper portion of the core layer 110 and formed with acircuit pattern including a wire bonding pad 140 aa, a second circuitlayer 140 b formed on the lower portion of the core layer 110 and formedwith a circuit pattern including a solder ball pad 140 ba, a via hole150 electrically connecting the upper and lower portions of the corelayer 110, a first solder resist layer 170 a stacked on the upperportion of the first circuit layer 140 a, a second solder resist layer170 b stacked on the lower portion of the second circuit layer 140 a,and a molding layer 180 covering the first solder resist layer 170 a.

In this configuration, the core layer 110 is configured to include twoinsulating layers 110 a and 110 b made of an insulating material.

The first insulating layer 110 a has one surface contacting the firstcircuit layer 140 a and includes a cavity 110 aa therein, wherein thecavity 110 aa has the semiconductor device 120 therein.

The second insulating layer 110 b is made of an insulating material andhas one surface contacting the first insulating layer 110 a and theother surface contacting the second circuit layer 140 b.

The first insulating layer 110 a and the second insulating layer 110 bmay be made of the same material or may be formed of differentmaterials.

Meanwhile, one surface of the core layer 110 is provided with solderballs 190 arranged in an array shape, wherein the solder balls areconnected to the solder ball pad 140 ba. It is mounted on a motherboard(not shown) through the solder ball 190.

When the solder balls 190 are connected to the solder ball pad 140 ba,they may be connected to the solder ball pad 140 ba, having an Ni/Auplating layer 140 bb therebetween.

Next, an example of the semiconductor device 120 mounted on the corelayer 110 may include a transistor, a diode, an IC chip, or the like.

The semiconductor device 120 is connected to the wire bonding pad 140 aaof the first circuit layer 140 a formed on the upper portion of the corelayer 110 through the wire 160.

The supporting layer 130 is formed to surround the semiconductor device120. In this case, the supporting layer 130 may be made of the samematerial as an insulating material of the second insulating layer 110 b.

The solder resist layers 170 a and 170 b are stacked on the firstcircuit layer 140 a or the second circuit layer 140 b and are providedwith a window for the wire bonding pad 140 aa or the solder ball pad 140ba.

Next, the molding layer 180 has the solder resist layer 170 a formed onthe upper portion thereof to serve to protect the semiconductor device120 from external environments or effects and firmly fixes thesemiconductor device 120 to the core layer 110.

As long as the material of the molding layer 180 is softened by heating,any materials may be used. As an example of a material of the moldinglayer 180, melamine derivatives, such as epoxy resin, BT resin, or thelike, liquid crystal polymer, PPE resin, polyimide resin, fluororesin,phenol resin, polyamide bismaleimide, etc., may be used. In addition,the molding layer 180 may include a filling agent, such as filler orfiber, or the like.

Meanwhile, the ball grid array substrate according to a first exemplaryof the present invention has only the circuit layer 140 a on the upperportion of the core layer 110, but may be configured to include aplurality of circuit layers by consecutively stacking the insulatinglayer and the circuit layer.

FIGS. 3 to 16 are process diagrams showing a manufacturing method of anembedded ball grid array substrate according to the first exemplaryembodiment of the present invention.

Referring to FIG. 3, in the embedded ball grid array substrate accordingto the first preferred embodiment of the present invention, a coppercladded laminate (CCL) in which copper clads 210 a and 210 b are stackedon a first insulating layer 200 is prepared.

In this case, there are various kinds of copper cladded laminates, suchas glass/epoxy copper cladded laminate, heat-resistant resin coppercladded laminate, paper/phenol copper cladded laminate, high-frequencycopper cladded laminate, flexible copper cladded laminate (polyimidefilm), and composite copper cladded laminate, or the like. Among others,the glass/epoxy copper cladded laminate is mainly used to manufacture aboth-side printed circuit board and a multi-layer printed circuit board.

As shown in FIG. 4, a cavity 220 is formed in the first insulating layer200 and a copper clad (herein, upper copper clad 210 a) of any one sideis removed. In this case, a method of forming the cavity 220 may beformed by a punching or drill bit.

Thereafter, as shown in FIG. 5, a heat-resistant tape 230 is stacked onone surface of the first insulating layer 200 formed with the cavity220. Herein, the heat-resistant tape 230 may use several materialsinsensitive to heat, preferably, a polyimide film.

Next, as shown in FIG. 6, the semiconductor device 240 is mounted in thecavity 220. In this case, the semiconductor device 240 is mounted sothat the wire bonding pad formed on a surface contacting theheat-resistant tape 230 of the first insulating layer 200 and the wiredbonding pad of the semiconductor device 240 electrically connectable toeach other by the wire face the heat-resistant tape 230 in thesubsequent process.

As shown in FIG. 7, the second insulating layer 250 b is stacked tocover the semiconductor device 240 and a copper clad 260 is stackedthereon, which is in turn compressed as shown in FIG. 8.

In this case, the second insulating layer 250 b may be a prepreg andwhen the second insulating layer 250 b is stacked to cover thesemiconductor device 240, a gap between the semiconductor device 240 andthe cavity 220 is filled with the second insulating layer 250 b to forma supporting layer 280 as can be appreciated from FIG. 8.

The copper clad 260 uses a carrier 270 when being stacked in the secondinsulating layer 250 b, such that it may be stacked in the secondinsulating layer 250 b. In this case, the carrier 270 is removed afterthe copper clad 260 is stacked in the second insulating layer 250 b. Inthis case, two insulating layers, i.e., insulating layers denoted byreference numerals 200 and 250 b form the core layer in the presentinvention.

Subsequently, the heat-resistant tape 230 is removed and the copper clad210 b is exposed on a surface from which the heat-resistant tape 230 isremoved.

Next, as shown in FIG. 9, in order to form the via hole electricallyconnecting the upper and lower surfaces of the insulating layers 200 and250 b, a through hole 290 is formed by being machined.

In this case, a process of forming the through hole may use a schemethat forms a through hole along a previously set position by using acomputer numerical control (CNC) drill or a laser drill.

Meanwhile, after forming the through hole 290, it is preferable toperform a desmear process that melts the insulating layers 200 and 250b, etc., due to heat generated at the time of forming the through hole290 to remove smear generated from a side wall of the through hole 290.

Thereafter, as shown in FIG. 10, the surfaces of the insulating layers200 and 250 b and the inner wall of the through hole 290 are providedwith copper plating layers 300 a and 300 b electrically connected toeach other by an electroless plating and an electroplating.

In this case, since the side wall of the through hole 290 of theinsulating layers 200 and 250 b is made of an insulating material, ancopper electroplating cannot be performed immediately after the throughhole 290 is formed.

Therefore, the electroless copper plating is performed in order toperform the electrical connection and electro copper plating of theformed through hole 290, thereby forming a copper electroplating layer300 a. After the electroless copper plating is completed, a copperelectroplating layer 300 b is formed by performing the copperelectroplating using a direct current rectifier after dipping theinsulating layers 200 and 250 b in a copper plating container.

It is preferable that the copper electroplating uses a scheme ofprecipitating copper with current suitable for the direct currentrectifier by calculating an area to be plated.

It is advantageous in that the copper electroplating has more excellentphysical characteristics than the electroless copper plating layer andmore easily forms the thick copper plating layer.

Next, as shown in FIG. 11, dry films 310 a and 310 b are each applied tothe upper and lower copper plating layers 300 a and 300 b of theinsulating layers 200 and 250 b.

In this case, the dry films 310 a and 310 b are formed of three layers,that is, a cover film, a photo-resist film, and a mylar film, whereinthe photo-resist film substantially serves as a resist.

Next, as shown in FIG. 12, a predetermined pattern is formed on the dryfilms 310 a and 310 b by exposing and developing the dry films 310 a and310 b on which a predetermined pattern is printed.

In this case, the predetermined pattern includes a circuit pattern, aland of a via hole E, a wire bonding pad pattern, and a solder ball padpattern.

The exposure and development process of the dry films 310 a and 310 badhere an art work film, on which a predetermined pattern is printed, tothe dry films 310 a and 310 b and then irradiate ultraviolet rays. Inthis case, ultraviolet rays do not transmit a black portion in which theart work film pattern is printed and ultraviolet rays transmit anon-printed portion, thereby curing the dry film under the art workfilm. If the insulating layers 200 and 250 b on which the dry films 310a and 310 b are cured is dipped in the developer, a portion in which thedry films 310 a and 310 b are not cured is removed by the developer anda portion in which the dry films 310 a and 310 b are cured remains,thereby forming the etching resist pattern.

As shown in FIG. 13, the upper and lower copper dads 210 b and 260 andthe copper plating layers 300 a and 300 b in a portion other than aportion corresponding to a predetermined pattern of the dry films 310 aand 310 b are removed through etching by using the dry films 310 a and310 b formed with the predetermined pattern as an etching resist andspraying an etchant to the insulating layers 200 and 250 b.

Thereafter, as shown in FIG. 14, the dry films 310 a and 310 b appliedto both surfaces of the upper and lower portions of the insulatinglayers 200 and 250 b are removed by a peeling off process and the solderresists 320 a and 320 b are applied and then pseudo-dried.

In this case, the dry films 310 a and 310 b are removed by using astripper including sodium hydroxide (NaOH) or potassium hydroxide (KOH),or the like.

In the process of FIGS. 11 to 14 as described above, the dry films 310 aand 310 b are used as the etching resist but may use a liquid-statephotosensitive material as the etching resist.

In this case, the liquid-state photosensitive material photosensitizedby ultraviolet rays is applied to the copper plating layers 300 a and300 b of the insulating layers 200 and 250 b and is dried. Subsequently,the photosensitive material is exposed and developed by using the artwork film on which a predetermined pattern is formed, thereby forming apredetermined pattern on the photosensitive material.

Next, the upper and lower copper dads 210 b and 260 and the copperplating layers 300 a and 300 b in a portion other than a portioncorresponding to a predetermined pattern of the photosensitive materialare removed through etching by using the photosensitive material formedwith the predetermined pattern as an etching resist and spraying anetchant to the insulating layers 200 and 250 b. Thereafter, thephotosensitive material is removed. In this case, as the method ofcoating the liquid-state photosensitive material, there are a dipcoating method, a roll coating method, an electro-deposition method, orthe like.

The method of using the liquid-state photosensitive material may applythinner than the dry films 310 a and 310 b, thereby making it possibleto form more finely circuit patterns. In addition, when there are ruggedportions on the insulating layers 200 and 250 b, the photosensitivematerial may fill the rugged portions to make the surface thereofuniform.

Meanwhile, the problem where the solder resists 320 a and 320 b and thecopper plating layer 300 b are not completely adhered to each other maybe caused.

Therefore, before the solder resists 320 a and 320 b are applied, it ispreferable to wash the surface of the substrate and perform pretreatmentgiving roughness on the surface of the substrate in order to improve theadhesion between the solder resists 320 a and 320 b and the copperplating layer 300 b.

As a method of applying the solder resists 320 a and 320 b, a screenprinting method, a roller coating method, a curtain coating method, aspray coating method, etc., may be used.

In this case, the screen printing method is a method of directlyprinting the solder resist pattern and the roller coating method is amethod of applying solder resist ink, which has lower viscosity thanthat used in the screen printing method, to a roller made of rubber andcoating it on the substrate.

In addition, the curtain coating method is a method of using the solderresist ink having viscosity lower than that used in the roller coatingmethod and the spray coating method is a method of spraying and coatingthe resist ink.

Next, after the art work film, on which the solder resist pattern isprinted, is adhered to the upper and lower solder resists 320 a and 320b, the solder resists 320 a and 320 b are exposed and developed, therebycuring the solder resists 320 a and 320 b corresponding to the solderresist pattern.

In this case, ultraviolet rays do not transmit the black portion inwhich the solder resist pattern of the art work film is printed duringthe exposure process and transmit the non-printed portion, therebycuring the solder resists 320 a and 320 b.

Thereafter, after the art work film is removed, the solder resists 320 aand 320 b in the non-cured portion are removed during the developmentprocess, thereby forming the solder resist pattern.

Thereafter, the UV-curing is made by irradiating ultraviolet rays andthe solder resists 320 a and 320 b are completely cured by using thedryer (not shown).

In the case, it is preferable to further perform a process of removingthe residuals, foreign materials, etc., of the solder resists 320 a and320 b remaining in the portion, in which the solder resists 320 a and320 b are removed, by plasma, or the like.

Next, as shown in FIG. 16, a Ni/Au plating layer 330 is formed in thesolder ball pad pattern.

Next, the semiconductor device 240 and the wire bonding pad are bondedand electrically connected to each other by using the wire 340, thesolder ball 350 is formed, and the molding 360 is then made, therebyforming the ball gray array substrate.

According to the present invention, the connection state of the embeddedcomponents can be checked by the naked eye by connecting between thesemiconductor devices and the wire bonding pads by the wire, therebymaking it possible to increase the connection reliability.

In addition, according to the present invention, the fine circuitpattern can be formed by connecting between the semiconductor devicesand the bonding pads by the wire.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims. Accordingly, suchmodifications, additions and substitutions should also be understood tofall within the scope of the present invention.

1-5. (canceled)
 6. A manufacturing method of an embedded ball grid arraysubstrate, comprising: (A) removing a copper clad of the firstinsulating layer, after preparing a copper cladded laminate formed witha copper clad at both sides of the first insulating layer and forming acavity; (B) attaching a heat-resistant tape to an opposite surface to asurface from which the copper clad of the copper clad laminate isremoved; (C) mounting a semiconductor device in a cavity of the copperclad laminate and stacking a second insulating layer and a copper cladon a surface from which the copper clad is removed; (D) forming a firstcircuit layer formed with a circuit pattern including a wire bonding padat a copper clad contacting the first insulating layer and forming acircuit pattern including a solder ball pad at a copper clad contactingthe second insulating layer; and (E) bonding and electrically connectingthe semiconductor device to a wire bonding pad by a wire.
 7. Themanufacturing method of the embedded ball grid array substrate as setforth in claim 6, further comprising after step (C), (F) forming a viahole penetrating through the first insulating layer and a secondinsulating layer.
 8. The manufacturing method of the embedded ball gridarray substrate as set forth in claim 6, further comprising after step(D), (G) stacking a first solder resist on a first circuit layer andstacking a second solder resist on a second circuit layer; (H) formingholes at a position corresponding to the wire bonding pad of the firstcircuit layer at the first solder resist; and (I) forming holes at aposition corresponding to the solder ball pad of the second circuitlayer at the second solder resist.
 9. The manufacturing method of theembedded ball grid array substrate as set forth in claim 6, wherein atstep (B), the heat-resistant tape is a polyimide film.
 10. Themanufacturing method of the embedded ball grid array substrate as setforth in claim 6, wherein step (C) includes: (C-1) mounting thesemiconductor device in the cavity of the copper clad laminate; (C-2)stacking the second insulating layer on a surface from which the copperclad is removed; (C-3) stacking the copper clad on the second insulatinglayer by using a carrier; and (C-4) removing the carrier.
 11. Themanufacturing method of the embedded ball grid array substrate as setforth in claim 6, wherein step (D) includes: (D-1) stacking a dry filmon a copper clad contacting the first insulating layer and a copper cladcontacting the second insulating layer; (D-2) forming a patterncorresponding to a circuit pattern of the first circuit layer includingthe wire bonding pad on the first dry film stacked on the copper cladcontacting the first insulating layer and forming a patterncorresponding to a circuit pattern of the second circuit layer includingthe solder ball pad on the second dry film stacked on the copper cladcontacting the second insulating layer; and (D-3) completing the firstcircuit layer and the second circuit layer formed with the circuit padincluding the wire bonding pad and the solder ball pad by etching thecopper clad according to the pattern of the first dry film and thesecond dry film.